1. Field of the Invention
The present invention relates generally to a dual switching power supply system free from any malfunction caused by coupling of the off noise of the voltage sensing signal in one switching power supply to the voltage sensing signal in the other switching power supply.
2. Description of the Prior Art
A dual switching power supply (SPS) system is primarily useful in a circuit that needs a variable voltage output. For example, in a multi-frequency monitor, the voltage required for different frequencies can vary from 60 volts to 150 volts. A set of power supplies with an extra control circuit may solve this problem, but this results in occupying more space and lower efficiency. Therefore a dual switching power supply system is utilized to overcome these disadvantages. This kind of system usually uses a current mode circuit with two SPSs and the two SPSs have to work at the same frequency to avoid interference. The two switch control signals in the two SPSs are on/off square waves. When they are in-phase and are working at the same frequency, the off noise of the voltage sensing signal with a shorter on-time (the time period when signal is "high") may disturb the voltage sensing signal with a longer on-time to an extent that the DC output voltage signal of the dual SPS system has severe ripples and causes instability. Such a phenomenon is found to be most obvious in the applications to monitor circuits because of the display of distorted pictures on the screen.
FIG. 1 shows a typical current mode dual switching power supply system for a monitor circuit. The frequencies of the two SPSs have to be the same as the horizontal synchronization (h-sync) signal of the monitor or the overall system will contain interference. The system includes at least two current mode control integrated circuits (IC) CON1 and CON2. Commercially available UC3842 of Unitrode Co. is an example of such an IC. Please refer to FIG. 2 for the waveforms and timing relations of the signals mentioned below. The width of the h-sync pulses is exaggerated and the signal is assumed to be an ideal square wave for easier understanding. The input AC voltage passes through a full-wave bridge rectifier RF, a high capacitance capacitor C.sub.h1 and then the transformer X1 to provide the desired level of output DC voltage. CON1 generates a control signal to control the on/off of the NMOS transistor Q1 which works as a switch. After CON1 is activated, capacitor C.sub.11 is charged up in a rate decided by the values of C.sub.11 and R1. Meanwhile, signal 111 at one end of C.sub.11 is detected by CON1 through pin #4 to see whether it is greater than a predetermined value V.sub.sense1. If so, the internal circuit of CON1 automatically lowers the voltage of signal 111 to zero, then C.sub.11 is charged up again and signal 111 starts a next cycle. Thus signal 111 is an oscillating saw wave. The input synchronization triggering signal h-sync from the monitor carries a square pulse passing through a filtering diode D1 and a differentiating capacitor C.sub.12, and results in an impulse signal 112 at the rising edge of the h-sync signal at node N.sub.1. The impulse adds to signal 111 and forces the voltage of signal 111 to exceed V.sub.sense1. When this happens, the voltage of signal 111 drops to zero right away and starts another cycle. Thus synchronizes signal 111 with the h-sync signal.
The gate terminal G.sub.1 of NMOS transistor Q1 is connected to pin #6 of CON1 to receive the switch control signal 113. Under the control of CON1, signal 113 goes to "high" when signal 111 falls to zero voltage. This turns on the transistor Q1 and the current passing through resister R.sub.s1 increases gradually because of the inductance of the coils of the transformer X1. The source terminal S.sub.1 of the NMOS transistor Q1, which is also the voltage sensing terminal, is connected to pin #3 of CON1. The voltage at S.sub.1, which is signal 114 in FIG. 2, is checked by CON1 to determine whether it is higher than a predetermined value V.sub.sense2. If so, the control IC CON1 turns off Q1 by dropping the voltage of signal 113 and the voltage at S.sub.1 to zero. Signals 111, 113 and 114 stay at zero voltage as the h-sync signal remains "low". The next cycle starts when the h-sync signal goes to "high" again. Therefore the frequencies of the switch control signal 113 and the voltage sensing signal 114 equal the frequency of the h-sync signal and the synchronization between the monitor and SPS1 is achieved.
Considering SPS2 at the bottom of FIG. 1, we can see that it is the same as SPS1 and receives the same h-sync signal for synchronization purpose. As a result, the switch control signal 123 at pin #6 of the control IC CON2 has the same frequency and phase as the switch control signal 113 and the h-sync signal from the monitor. Thus the synchronization process between the monitor, SPS1 and SPS2 is complete.
However, because of probable different loading requirements for the two SPSs, the two switch control signals at the two gate terminals, i.e. signal 113 and 123, may have a different duration of on-times. For convenience, assume that the on-time of signal 113 is shorter than that of signal 123 as shown in FIG. 2. The switching and state changing of the NMOS transistors and the transformers induce noise in the transient states of the two voltage sensing signals. Due to ground and other wiring on the printed circuit board (PCB), noise of one voltage sensing signal couples to the other voltage sensing signal. This can be observed from FIG. 2. Because the two on times are not of equal duration, the off noise of signal 114 couples onto the slope portion of signal 124 and, depending on the amplitude of the noise and the difference between the duration of two on-times, it may push the voltage of signal 124 to a level higher than V.sub.sense2 and force signal 123 to go "low" before the moment it is designed to if noise is not present. This turns off the NMOS transistor Q2 prematurely and causes the output of the power supply system to be unstable. Prior art solutions to this problem include reducing the amplitude of the off noise and better PCB layout processing. However, difficulties still exist and the result may not be satisfactory even when great care is exercised.